1. Field of the Invention
The present invention relates to semiconductor processing, and more particularly to a method of forming an emitter of a bipolar device.
2. Prior Art
While conventional CMOS (Complementary Metal Oxide Semiconductor) integrated circuit processes may be used to create circuits which consume less power and occupy less space on a semiconductor substrate than similar circuits designed around a bipolar transistor fabrication process, bipolar devices, among other advantages, have the inherent ability to operate at higher speeds than MOS (Metal Oxide Semiconductor) devices. In an attempt to capture the advantages of both bipolar and MOS devices in one circuit, a BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process has been developed. In a BiCMOS process, bipolar and MOS transistors are both created on a single semiconductor substrate so that a portion of the resulting circuit operates using bipolar transistors while another portion of the same circuit operates using MOS transistors. The result is a circuit which, among other advantages, consumes very little power, occupies very little space, and operates at very high speeds. A circuit such as this would have extensive applications in, for instance, battery-powered notebook computers where power consumption must be minimized in order to prolong battery life, size must be minimized to enhance portability, and processing speeds must be fast enough to handle advanced computational applications.
Process techniques for creating MOS transistors have been well developed in the art as have process techniques for creating Bipolar transistors. The combination of the two processes, however, have presented unique considerations to be weighed within the BiCMOS manufacturing environment. Generally, BiCMOS processes are built around a CMOS process base. Additional processing steps must be added to the basic CMOS process in order to incorporate bipolar transistors in the finished product. Usually 3 or 4 additional masking steps are required to convert a CMOS process into a BiCMOS process. These additional masking steps contribute to increased process throughput time and decreased product yield. The result is that the manufacturing costs associated with BiCMOS processes are much increased over conventional CMOS processes.
In order to make BiCMOS devices commercially viable, it is necessary to minimize this manufacturing cost as much as possible by, for instance, either decreasing process throughput time or decreasing product loss due to contamination thereby improving product yield. Attempts to increase process throughput time is two-faceted. First, the process steps in BiCMOS processes have been minimized by design. The basic CMOS processes upon which BiCMOS processes are built are becoming progressively more complex and time consuming, and with each new level of complexity, the CMOS process sequence is redesigned to cut as much time out of the total manufacturing budget as possible. The fact remains, however, that no matter how the manufacturing sequence of a basic CMOS process is minimized, 3 to 4 additional masking steps are expected to always be required to convert a CMOS process into a BiCMOS process. Second, the process equipment used in the manufacture of CMOS and BiCMOS products is continually being improved to minimize throughput time and feature sizes of the products. Unfortunately, the equipment costs associated with CMOS and BiCMOS processes have been increasing at an exponential rate with respect to advancing generations of these processes. Therefore, for general CMOS and BiCMOS device applications, it is most cost effective to squeeze the maximum possible yield out of each generation of the manufacturing process before moving to the next.
Improving product yield by minimizing product loss due to contamination, like increasing process throughput time, is also two-faceted. First, product yield may be improved by reducing the overall level of foreign particulates and chemicals which exist within the manufacturing environment. This foreign matter may contaminate the BiCMOS devices and cause them to become inoperable. In order to reduce the overall level of contaminants within the manufacturing environment, much expense must be invested into filtering the air, cleaning the process equipment, using only ultra-pure chemicals, implementing stringently clean processing procedures, etc. Unfortunately, each successive generation of BiCMOS processes lowers the tolerable level of contamination within the manufacturing environment. Thus, significant sums of money must be spent in order to lower the amount of contamination to acceptable levels with the introduction of more advanced BiCMOS processes. Second, product yield may be improved by, wherever possible, utilizing various compounds and structures in the BiCMOS process which make the BiCMOS devices more tolerable to contamination. This way, as BiCMOS processes advance to new generations, the manufacturing environments may not need to advance to the same degree.
A bipolar transistor consists of two pn junction diodes in very close proximity. If the diodes are connected with their p-type regions facing each other, the bipolar transistor is denoted npn. If the diodes are connected with their n-type regions facing each other, the bipolar transistor is denoted pnp. Of the three regions in a bipolar transistor, the center region is called the base and is sandwiched between the outer two regions called the emitter and the collector. The current flow between the emitter and collector is controlled by the voltage applied to the base. To use a bipolar transistor for digital applications, a nominal voltage applied to the base is used to either turn "on" or "off" the emitter/collector "switch." Under steady-state biasing conditions in a bipolar transistor "off" state, the base region electrically isolates the emitter from the collector. Under steady-state biasing conditions in a bipolar transistor "on" state, the base region allows relatively unimpeded electrical current to flow between the emitter and the collector.
FIG. 1 shows a cross section of a simplified bipolar transistor. The electrical nodes 10, 11, and 12 are shown connected to emitter 16, base 17, and collector 18 regions respectively. Assuming this bipolar transistor to be npn, the emitter 16 is doped n-type, the base 17 is doped p-type, while the collector 18 is doped n-type. For electrical isolation, this bipolar transistor might be built inside a p-type well 21. The oxide masking layer 23 defines the contacts to the underlying bipolar regions. A portion of field oxide 22 is also shown in FIG. 1. In a bipolar transistor built into a semiconductor substrate, as shown in FIG. 1, the width of the base is typically defined as the minimum distance an electrical current must travel through the base in order to bridge the emitter to the collector. In FIG. 1, this minimum distance is the vertical distance through the base between the emitter 16 and the collector 18 as denoted by line 24.
Several methods have been developed to manufacture bipolar transistors. Generally, the emitter, base, and collector regions are formed by ion implantation of dopants into the semiconductor substrate. These regions are then individually contacted at the surface of the semiconductor substrate and become part of a complete circuit. In more advanced bipolar structures, the emitters are created by diffusion of a dopant from a polysilicon layer which is deposited directly onto the semiconductor substrate surface. It has been demonstrated that these polysilicon emitter, bipolar transistors exhibit current gains which are approximately five times greater than their implanted emitter counterparts. This increased current gain allows for narrower base widths to be incorporated into the transistor while still maintaining proper emitter to collector electrical isolation by increasing the doping concentration of the base region. Also, polysilicon emitter processes allow for better control of the emitter depth into the semiconductor substrate which allows for more precise narrowing of the base width. The narrower the base width becomes, the faster the transistor can switch on and off. Thus, polysilicon emitters, among other advantages, allow bipolar transistors to operate at higher speeds in digital circuits. If the base region becomes too narrow, however, the emitter to collector electrical isolation will be lost, and a phenomenon known as punchthrough will occur rendering the bipolar transistor inoperative.
Polysilicon emitters also allow the vertical and lateral dimensions of an emitter to be scaled in a coordinated manner which keeps the emitter-base junction capacitance to a reasonable value. Also, polysilicon emitters do not suffer from many of the yield problems associated with implanted emitters. For example, implanted emitters maintain lattice defects in the semiconductor substrate even after annealing due to damage from ion-bombardment during the ion implantation process. Instead, polysilicon emitter dopants are diffused into undamaged silicon so no lattice defects are created. Additionally, polysilicon emitters do not risk reliability and yield problems associated with contact spiking. Contact spiking can be a problem when implanted emitters are connected at the semiconductor substrate surface by aluminum or aluminum alloys.
FIG. 2 shows the emitter region of FIG. 1 with a polysilicon emitter replacing the implanted emitter of FIG. 1. FIG. 2 shows the polysilicon 30 which has diffused dopant into the semiconductor substrate in order to form the emitter 32 within the base 33 which in turn is within the collector 34. Assuming that the resultant bipolar transistor is of type npn, the emitter 32 is highly doped n-type, the base 33 is p-type, the collector 34 is n-type and the well 35 in which the bipolar transistor has been formed is p-type. The emitter mask 31, comprising silicon dioxide, is shown along with a portion of a field oxide region 36. Note that the polysilicon layer 30 extends beyond the lateral encroachment of the actual emitter region 32 above the base region 33 and the emitter mask 31. The emitter mask 31, therefore, protects the bipolar transistor from electrically shorting the emitter-base junction. For instance, if an electrical breakdown occurred in the emitter mask 31 anywhere under the polysilicon layer 30, the voltages applied to the base region 33 would be transferred directly to the polysilicon emitter. An electrical breakdown such as this would destroy the transistor action of the bipolar device. Any significant defects or contaminants in the emitter mask 31, particularly at the polysiliconoxide interface, may cause such a breakdown to occur thereby potentially rendering the bipolar device inoperative. Therefore, it is necessary to keep the emitter mask 31 immaculately clean and free from all defects.
In a typical BiCMOS process, it is difficult to maintain the cleanliness of this emitter mask 31 because it is subjected to many harsh process environments. For instance, the application and stripping of the photoresist which defines the emitter window in the emitter mask, and the polysilicon preclean steps which usually precede polysilicon deposition can leave defects and contaminants in the emitter mask at the polysilicon-oxide interface. Upon operation of a bipolar transistor, these defects and contaminants serve as catalysts to the electrical breakdown of the emitter mask 31 between the polysilicon emitter 30 and the base region 33. As stated above, the occurrence of such a breakdown may render the bipolar device inoperative thus lowering product yield.
In FIG. 2, the base width is denoted as distance 37. As mentioned earlier, if the base width 37 is too large, bipolar transistor switching speed will be degraded. If the base width 37 becomes too small, emitter 32 to collector 34 punchthrough will occur. It is therefore necessary to accurately maintain the base width to exacting tolerances. Unfortunately, since the base region 33 is implanted through the emitter mask 31 prior to patterning of the emitter window in the emitter mask 31, variations in emitter mask 31 thickness will be shadowed by variations in base implant depth into the semiconductor substrate. There are generally three components which contribute to emitter mask thickness variation. First, there is variation across the surface of a single semiconductor substrate (generally referred to as die level variation). Second, there is variation across multiple semiconductor substrates processed together at the same process step (generally referred to as wafer level variation). Third, there is variation across multiple semiconductor substrates processed separately at the same process step (generally referred to as lot level or batch level variation).
FIGS. 3a and 3b show slices from two different semiconductor substrates at the same processing step during a BiCMOS process. The slices were taken through what will become the emitter region of a bipolar transistor. The semiconductor slice depicted in FIG. 3a comprises a collector region 40, an emitter mask 43, and a base region 42 which has been implanted through the emitter mask 43. The semiconductor slice depicted in FIG. 3b comprises a collector region 44, an emitter mask 46, and a base region 45 which has been implanted through the emitter mask 46. Note the difference between the two slices in FIGS. 3a and 3b in base region depth into the semiconductor substrate. In FIG. 3a, the base region depth 55 is much shallower than the base region depth 56 of FIG. 3b. This difference is due to the difference in emitter mask thicknesses. The thicker the oxide emitter mask, the less distance an implanted ion will travel beneath the oxide-silicon interface since the ion's velocity is significantly slowed by the emitter mask layer.
FIGS. 4a and 4b show the same semiconductor substrate slices of FIGS. 3a and 3b respectively after the emitter windows have been etched into the emitter mask. Note that the emitter windows are etched such that the bottom of the windows exist at the surface of the base regions of the semiconductor substrate. Because the semiconductor substrate behaves as an etch stop to the emitter window etch, the base region depth 55 in FIG. 4a and the base region depth 56 in FIG. 4b remain unchanged from the base region depths in FIGS. 3a and 3b respectively. Hence, the difference in base region depths between the two semiconductor slices is propagated on to the next step in the BiCMOS fabrication process.
FIGS. 5a and 5b show the same semiconductor substrate slices of FIGS. 4a and 4b after the polysilicon has been deposited and emitters have been created. The semiconductor slice in FIG. 5a now comprises a polysilicon layer 48 and a diffused emitter region 50. The semiconductor slice in FIG. 5b also comprises a polysilicon layer 47 and an emitter diffused region 52. The actual base width 57 of FIG. 5a is now apparent as is the base width 58 of FIG. 5b. Note the difference in the base widths between the two slices. This difference is a direct result of the difference in the emitter mask thicknesses of FIGS. 3a and 3b which caused the different base implant depths beneath the semiconductor substrate surface. This difference in base widths can result in either inoperative, or unreliable bipolar transistors which will lower product yield. In the case of FIG. 5a, the base width 57 may be too narrow to provide proper emitter 50 to collector 40 isolation which will result in punchthrough. In the case of FIG. 5b, the base width 58 may be too large to allow for the necessary switching speeds. Finally, because a BiCMOS process which allows such a large variation in base widths will produce unpredictable circuits, it becomes difficult, if not impossible, to design complex systems around these processes.
In typical BiCMOS bipolar transistors, the base doping profile is graded such that the maximum doping concentration exists near the surface of the base, near the boundary between the emitter mask 31 and the base region 33 in FIG. 2. Under electrical bias, the high doping concentration of the base in conjunction with the high doping concentration of the emitter causes a very strong electric field to exist at the emitter-base pn junction. These strong electric fields lead to hot electron generation. If the hot electrons are generated in the vicinity of an oxide, a certain percentage of electrons will be injected into that oxide and become trapped. These trapped electrons then have the potential to adversely affect the electrical characteristics of the bipolar device.
Note that the lateral edges of the diffused emitter region 32 in FIG. 2 are in mutual contact with both the surface of the base region 33 and the emitter mask 31. Therefore, the hot electrons generated at the lateral edges of the diffused emitter region have the potential to be injected into the emitter mask 31 and become trapped there. These trapped electrons can then degrade the performance of the bipolar transistor thereby causing yield and reliability problems. Note that silicon substrate cleaning processes may remove a portion of the silicon substrate in the emitter window prior to depositing the polysilicon. These cleaning processes, while perhaps causing a very shallow emitter trench in the silicon substrate, are generally not sufficient to move the strong electric field far enough away from the emitter mask to avoid the deleterious effects of hot electron injection into the emitter mask.